1 tm file number 3041.3 hs-82c12rh radiation hardened 8-bit input/output port the intersil hs-82c12rh is a radiation hardened 8-bit input/output port designed for use with the hs-80c85rh radiation hardened microprocessor. it is manufactured using a self-aligned, junction-isolated epi-cmos process and features three-state output buffers and device selection and control logic. a service request ?p-?p is included for the generation and control of interrupts to the microprocessor. the device can be used in implement many of the peripheral and input/output functions of a microcomputer system. the hs-82c12rh is pinout- and function- compatible with industry-standard 8212 devices. speci?ations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical speci?ations for these devices are contained in smd 5962-95818. a ?ot-link?is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp features electrically screened to smd # 5962-95818 qml quali?d per mil-prf-38535 requirements radiation performance - hardened epi-cmos process - total dose. . . . . . . . . . . . . . . . . . . . . 100 krad(si) (max) - transient upset . . . . . . . . . . . . . . . . . > 1 x 10 8 rad(si)/s - latch-up immune low power dissipation high noise immunity single power supply . . . . . . . . . . . . . . . . . . . . . . . . . +5v low input load current 8-bit data register and buffer asynchronous register clear service request flip-flop for interrupt generation three-state outputs bus-compatible with hs-80c85rh cpu electrically equivalent to sandia sa3026 military temperature range . . . . . . . . . . . -55 o c to 125 o c functional diagram ordering information ordering number internal mkt. number temp. range ( o c) 5962r9581801qjc hs1-82c12rh-8 -55 to 125 5962r9581801qxc hs9-82c12rh-8 -55 to 125 5962r9581801v9a HS0-82C12RH-Q 25 5962r9581801vjc hs1-82c12rh-q -55 to 125 5962r9581801vxc hs9-82c12rh-q -55 to 125 pin description pin description di0-di7 data in do0-do7 data out ds1, ds2 device select md mode stb strobe int interrupt clr clear control and device select logic data latch and buffer (8) 2 3 int ds2 stb md ds1 service request f. f. di0-7 do0-7 clr data sheet august 2000 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000
2 pinouts 24 lead ceramic dual-in-line metal seal package (sbdip) mil-std-1835 cdip2-t24 top view 24 lead ceramic metal seal flatpack package (flatpack) mil-std-1835 cdfp4-f24 top view 1 2 3 4 5 6 7 8 9 10 11 12 ds1 md di0 do0 di1 do1 di2 do2 di3 do3 stb gnd 16 17 18 19 20 21 22 23 24 15 14 13 vdd di7 do7 di6 do6 do5 do4 clr ds2 int di5 di4 24 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 12 1 gnd ds1 md di0 do0 di1 do1 di2 do2 di3 do3 stb vdd ds2 clr do4 di4 do5 int di7 do7 di6 di5 do6 hs-82c12rh
3 timing waveforms figure 1. read timing figure 2. write timing figure 3. data setup, hold, propagation delay timing figure 4. interrupt timing figure 5. clear timing ( ds, ? ds2) output te td 0.5vdd 0.5vdd voh vol data md or ( ds, ? ds2) output tpw th twe data stb or ( ds, ? ds2) output tset th tpd stb ( ds, ? ds2) int tpw tr tpw ts clr do tpw tc hs-82c12rh
4 functional description data latch the data latch is comprised of eight ??type ?p-?ps. the output of each ?p-?p will follow the corresponding data input (di0 - di7) when the clock (c) is high. the clock input is level sensitive and the data becomes latched when the clock returns low. an asynchronous reset ( clr) is used to clear the latched data. since the clock (c) overrides the reset ( clr), the data must be in the latched state in order to clear the ?p-?ps. if the data is not latched (i.e. clock is high) when clr goes low, then the q outputs of the data latch will continue to follow the data input, overriding the reset signal. output buffer three-state buffers are used to provide output drive for the data latch. a high level on the ?utput buffer enable?control line enables the buffer outputs. when ?utput buffer enable is low the buffer outputs are forced to the high-impedance state. device select logic the inputs ds1 and ds2 are used for device selection. when ds1 is low and ds2 is high, the device is selected. the output buffers are enabled and the service request ?p- ?p is asynchronously cleared when the device is selected. mode the mode input (md) is used to control the state of the output buffer and to determine the source of the data latch clock (c). when md is high, the output buffers are enabled and the source of the data latch clock (c) is the device select logic ( ds1 ? ds2). when md is low, the state of the output buffer is controlled by the device select logic ( ds1 ? ds2) and the source of the data latch clock is the strobe (stb) input. strobe the strobe input (stb) is used as the data latch clock (c) when the mode input (md) is low. the service request ?p- ?p is synchronously set on the negative going edge of stb. service request flip-flop the service request ?p-?p is to generate interrupts to microcomputer systems. it is negative edge triggered and asynchronously cleared (reset). the output of the service request ?p-?p is and-gated with the device select logic ( ds1 ? ds2). the output of the and gate is the active low interrupt ( int) signal. hs-82c12rh
5 logic diagram ds1 ds2 13 device select s d q c q service request flip-flop stb 11 clr 14 md 2 latch reset di0 dq e q r 3 tsb data out enable do0 4 di1 dq e q r 5 tsb do1 6 di2 dq e q r 7 tsb do2 8 di3 dq e q r 9 tsb do3 10 di4 dq e q r 16 tsb do4 15 di5 dq e q r 18 tsb do5 17 di6 dq e q r 20 tsb do6 19 di7 dq e q r 22 tsb do7 21 int 23 latch clock table 1. data out stb md ds1 ? ds2 data out equals 0 0 0 high z state 1 0 0 high z state 0 1 0 data latch 1 1 0 data latch 0 0 1 data latch 1 0 1 data in 0 1 1 data in 1 1 1 data in t able 2. int clr ds1 ? ds2 stb (note) q int 0 reset 0001 10001 10 10 1 1 reset 0 0 0 10001 note: internal service request flip-flop hs-82c12rh
6 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 die characteristics die dimensions: 90 mils x 76 mils x 14 mils 1 mil interface materials: glassivation: type: sio2 thickness: 8k ? 1k ? top metallization: type: alsi thickness: 11k ? 2k ? substrate: radiation hardened silicon gate, dielectric isolation backside finish: silicon assembly related information: substrate potential: unbiased (di) metallization mask layout hs-82c12rh (22) di7 (21) do7 (20) di6 (19) do6 (18) di5 (17) do5 (16) di4 (15) do4 do3 (10) stb (11) gnd (12) ds2 (13) clr (14) do0 (4) di1 (5) do1 (6) di2 (7) do2 (8) di3 (9) (3) di0 (2) md (1) ds1 (24) vdd (23) int hs-82c12rh
|
